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  • ASIC Logic Verification Engineers (Senior and entry levels)

    职位信息
    工作性质:全职
    工作地点:天津市

    职位描述
    ASIC Logic Verification Engineers (Senior and entry levels)

     Functions:
    • Develop the infrastructure and test-bench for the validation of RTL design.
    • Develop directed and random tests.
    • RTL simulation and hardware emulation.
    • Lead the process/methodology development and execution.

    Requirements:
    • Solid knowledge of semiconductor logic design and flow.
    • Strong programming skills (C/C++/SystemC/Verilog).
    • Fluent in UNIX script programming (Perl/ TCL/bash/csh).
    • Have developed verification environment(s) and test cases.
    • Extensive RTL development experience (Verilog or VHDL) is a plus.
    • Good communication skills and presentation skills, easy to work with.
    • Detail oriented, methodical.
    • Fluent in English. Able to read, write and interpret English specifications and documents accurately.
    • BS, MS or Ph.D. degree in Computer Science or Electrical Engineering.

    温馨须知:
    1、 履历投递说明:
    为提高履历处理效率,目前先接受电子履历应征方式。履历投递步骤如下:
    Step1:将完整电子履历文件名保存为“姓名_应征职位”。
    Step2:将履历以电子邮件附件方式发送至jing.shi@norelsys.com
    邮件主题格式为:
    [2010应届][应聘职位][学校科系][学历][姓名][联系电话]
    范例:[2010应届][数字芯片][X学校X系][硕士][张大力][13XXXXXX]
    切勿将履历直接贴于邮件正文内。


  • Software Engineer

    职位信息
    工作性质:全职
    工作地点:天津市

    职位描述
    Functions:
    • Develop USB drivers for Microsoft Windows OS (XP, Vista, Windows 7).
    • Develop and maintain GUI software on PC for hardware debugging board and OEM customization tool.
    • Work with hardware development team to bring up and debug new products.
    • Customize software to suit OEM’s need.

    Requirements
    • Familiar with PC hardware, Microsoft Windows OS (XP, Vista, Windows 7) as well as embedded systems.
    • Solid background in C and C++.
    • Extensive experience with user interface development using Win32 API.
    • Familiar with USB driver development on Windows OS (XP, Vista, Windows 7).
    • MS in CS or EE, or BS plus 4 years of related experience.

    温馨须知:
    1、 履历投递说明:
    为提高履历处理效率,目前先接受电子履历应征方式。履历投递步骤如下:
    Step1:将完整电子履历文件名保存为“姓名_应征职位”。
    Step2:将履历以电子邮件附件方式发送至jing.shi@norelsys.com
    邮件主题格式为:
    [2010应届][应聘职位][学校科系][学历][姓名][联系电话]
    范例:[2010应届][数字芯片][X学校X系][硕士][张大力][13XXXXXX]
    切勿将履历直接贴于邮件正文内。


  • Analog and Mixed-signal Design Engineer(Senior and entry levels)

    职位信息
    工作性质:全职
    工作地点:天津市

    职位描述
    Analog and Mixed-signal Design Engineer(Senior and entry levels)

    Functions: 
    • Analysis, design, and characterization of high speed (1-6Gb/s) analog and mixed-signal integrated circuits for wireline applications, such as PLL, VCOs, high speed I/O, equalizer, SERDES, CDR, etc.
    • Work on block level mixed signal integration and verifications.
    • Supervise layout of analog circuits.
    • Must be strong individual contributor and also able to work as member of a small team.

    Requirements:
    • Industry experience in design of analog and mixed-signal blocks, and advanced design skills in some of the following areas:
    (a). PLL/DLL, regulators, VCOs, etc.
    (b). high speed (multi-Gbps) interfaces, wireline driver, receiver, equalizer, etc.
    (c). high speed SERDES, CDR.
    • Extensive experience with design and layout tools such as Cadence Virtuoso, Cadence Spectre-RF, HSPICE, or other similar simulators and layout tools.
    • Good understanding of semiconductor devices and technology.
    • Experience in IC design verification and testing.
    • Experience in testing and characterization of high speed ICs is a plus.
    • Knowledge of Matlab/Verilog modeling of analog circuits such as PLL and CDR is a plus.
    • MS or Ph.D. degree in Electrical Engineering.

    温馨须知:
    1、 履历投递说明:
    为提高履历处理效率,目前先接受电子履历应征方式。履历投递步骤如下:
    Step1:将完整电子履历文件名保存为“姓名_应征职位”。
    Step2:将履历以电子邮件附件方式发送至jing.shi@norelsys.com
    邮件主题格式为:
    [2010应届][应聘职位][学校科系][学历][姓名][联系电话]
    范例:[2010应届][数字芯片][X学校X系][硕士][张大力][13XXXXXX]
    切勿将履历直接贴于邮件正文内。


  • ASIC Design Manager

    职位信息
    工作性质:全职
    工作地点:天津市

    职位描述
    ASIC Design Manager

    Functions
    - Manage the development of complex ASIC chips

    Requirements:
    - Management, technical leadership and mentoring skills
    - Experienced in the ASIC design flow, DFT, timing analysis, floor planning, ECO flow, STA, Silicon bring up flow
    - Experience in flat and hierarchical top-down P&R flows
    - Experience in logic design, synthesis, functional & timing verification skills
    - Familiar with Perl or TCL
    - Proven tape-out experience
    - 6+ years relevant work experience
    - M.S. or Ph.D. in Electrical Engineering or Computer Science.
    温馨须知:
    1、 履历投递说明:
    为提高履历处理效率,目前先接受电子履历应征方式。履历投递步骤如下:
    Step1:将完整电子履历文件名保存为“姓名_应征职位”。
    Step2:将履历以电子邮件附件方式发送至jing.shi@norelsys.com
    邮件主题格式为:
    [2010应届][应聘职位][学校科系][学历][姓名][联系电话]
    范例:[2010应届][数字芯片][X学校X系][硕士][张大力][13XXXXXX]
    切勿将履历直接贴于邮件正文内。


  • Digital ASIC Verification Engineer (Senior and entry levels)

    职位信息
    工作性质:全职
    工作地点:天津市

    职位描述
    Digital ASIC Verification Engineer (Senior and entry levels)

    Functions:
    • Develop the infrastructure and test-bench for the validation of RTL design.
    • Develop directed and random tests.
    • RTL simulation and hardware emulation.
    • Lead the process/methodology development and execution.

    Requirements:
    • Solid knowledge of semiconductor logic design and flow.
    • Strong programming skills (C/C++/SystemC/Verilog).
    • Fluent in UNIX script programming (Perl/ TCL/bash/csh).
    • Have developed verification environment(s) and test cases.
    • Extensive RTL development experience (Verilog or VHDL) is a plus.
    • Good communication skills and presentation skills, easy to work with.
    • Detail oriented, methodical.
    • Fluent in English. Able to read, write and interpret English specifications and documents accurately.
    • BS, MS or Ph.D. degree in Computer Science or Electrical Engineering.

    温馨须知:
    1、 履历投递说明:
    为提高履历处理效率,目前先接受电子履历应征方式。履历投递步骤如下:
    Step1:将完整电子履历文件名保存为“姓名_应征职位”。
    Step2:将履历以电子邮件附件方式发送至jing.shi@norelsys.com
    邮件主题格式为:
    [2010应届][应聘职位][学校科系][学历][姓名][联系电话]
    范例:[2010应届][数字芯片][X学校X系][硕士][张大力][13XXXXXX]
    切勿将履历直接贴于邮件正文内。


  • ASIC Logic Design Engineers (Senior and entry levels)

    职位信息
    工作性质:全职
    工作地点:天津市

    职位描述
    ASIC Logic Design Engineers (Senior and entry levels)

    Functions:
    • Develop micro-architecture based on specification and customer input.
    • Develop implementation spec for sub-blocks.
    • Verilog design, DFT and timing closure.
    • Block level verification and FPGA prototyping.

    Requirements:
    • Solid knowledge of semiconductor logic design and flow, familiar with Synthesis and Static Timing Analysis.
    • Strong programming skills (C/C++/SystemC/Verilog).
    • Familiar with UNIX environment Perl/ TCL/bash/csh.
    • Strong analytical and problem solving capability.
    • Good communication skills and presentation skills, easy to work with.
    • Detail oriented, methodical.
    • Able to read and interpret English specifications and documents accurately.
    • BS, MS or Ph.D. degree in Computer Science or Electrical Engineering.

    温馨须知:
    1、 履历投递说明:
    为提高履历处理效率,目前先接受电子履历应征方式。履历投递步骤如下:
    Step1:将完整电子履历文件名保存为“姓名_应征职位”。
    Step2:将履历以电子邮件附件方式发送至jing.shi@norelsys.com
    邮件主题格式为:
    [2010应届][应聘职位][学校科系][学历][姓名][联系电话]
    范例:[2010应届][数字芯片][X学校X系][硕士][张大力][13XXXXXX]
    切勿将履历直接贴于邮件正文内。


  • Signal Integrity Engineer

    职位信息
    工作性质:全职
    工作地点:天津市

    职位描述
    Signal Integrity Engineer

    Functions:
    - Responsible for signal integrity design and characterization of GHz high-speed serial link channel.
    - Perform signal integrity design and characterization of chip and board design.
    - The job includes but not limits to: signal integrity & power integrity analysis, package design and BER (Bit Error Rate) test.

    Requirements:
    - Familiar with Spice, ADS, HFSS and so on
    - Knowledge of signal integrity and power integrity
    - Familiar with high speed serial link technologies is a plus
    - M.S. or Ph.D. in Electrical Engineering or equivalent, Ph.D. is preferred.
    - Background in RF or Microwave is a plus.

    温馨须知:
    1、 履历投递说明:
    为提高履历处理效率,目前先接受电子履历应征方式。履历投递步骤如下:
    Step1:将完整电子履历文件名保存为“姓名_应征职位”。
    Step2:将履历以电子邮件附件方式发送至jing.shi@norelsys.com
    邮件主题格式为:
    [2010应届][应聘职位][学校科系][学历][姓名][联系电话]
    范例:[2010应届][数字芯片][X学校X系][硕士][张大力][13XXXXXX]
    切勿将履历直接贴于邮件正文内。