Introduction

The NS6112 serializer chip is compliant to Automotive Wired High-Speed Media Transmission (HSMT) standard. Pairing with a compatible HSMT deserializer, the NS6112 is used for transmission of forward video and bidirectional audio and control data. The NS6112 converts a single or dual MIPI CSI inputs to serialized HSMT output, and transmits the output to the paired deserializer over a single or dual HSMT links. Each HSMT link operates at a data rate up to 6.4Gbps in the forward direction and 100Mbps in the backward direction. The NS6112 supports Power-over-Cable (PoC) operation with 16m Coaxial cable or 10m STP cable, with multiple inline connectors. The NS6112 is ISO 26262 ASIL-B and AEC-Q100 Grade 2 certified with automotive temperature range of -40°C to +105°C, and compliant with ISO 10605 and IEC 61000-4-2 ESD standards.

The NS6112 supports I2C and SPI control ports, flexible GPIO with trigger mode, constant latency mode and oversample mode, tunneled UART, forward and backward audio channels, a built-in ADC, temperature sensor, and an extensive set of diagnostics for functional safety.

Applications

·         High-Definition 12MP Camera Systems

·         Advanced Driver Assistance Systems (ADAS)

·         Front Vision Camera Systems (FVC)

·         Surround View Systems (SVS)

·         Driver Monitor Systems (DMS)

·         Automatic Parking Assist (APA)

Features

·         Two HSMT links for system and power flexibility

·        2.0, 3.2, 4.0, or 6.4Gbps forward-link rates per link

·        100Mbps backward-link rate to allow small POC inductor

·         Robust communication in automotive environment

·        RS-FEC for protection of forward video and bidirectional control-channel data

·        Retransmission

·        Backward channel adaptive equalization

·        Backward channel eye timing margin monitor for continuous link margin diagnosis

·         Single or dual MIPI CSI-2 input ports

·        RAW8/10/12/14/16/20/24, RGB888, YUV422 8/10-bit

·        16 virtual channels

·        D-PHY v1.2 with 1/2/4 data lanes per port

·        Supports 80Mbps-2.5Gbps/lane

·         Supports bulk and tunneling modes I2C (master up to 833Kbps, slave up to 1Mbps)

·         Supports SPI (master/slave up to 50Mbps), UART (Tx/Rx), and GPIO

·         Digital audio with I2S and TDM interface

·        Supports forward-direction 7.1 HD audio and up to 192kHz sample rate

·        Supports backward-direction 8 channels at 48kHz sample rate or 2 channels at 192kHz sample rate

·         ISO 26262 ASIL-B and AEC-Q100 Grade 2 certified

·         CRC protection of control-channel data (I2C and SPI)

·         Video data error correction and retransmission

·         Video watermark and video test pattern generation

·         Supports line fault detection and voltage monitor

·         Generates reference clock for image sensor synchronizing to back channel clock

·         Generates frame sync singal to image sensor

·         Programmable spread spectrum for EMI reduction

·         9mm x 9mm 64-pin QFN package